● Poor board design for high dI/dt applications (e.g. DC/DC)
● Poorly chosen bias levels for continuity testing (e.g. mAs of current forced)
● Poor grounding resulting in excessive noise on the ground plane.
● Uncontrolled voltage surge on the power supply
● ESD events that trigger a larger EOS event or cause damage that weaken the device making it more susceptible to future EOS events
● Latch-up events may result in EOS damage if the current is high or if it persists for an extended time period